Development boards
Board-specific settings that are not derivable from the part number. Panel
Cache and memory barriers
The L1 caches exist on Cortex-M7 cores (STM32F7, H7). On M3, M4 and M33 the
Clock configuration
SystemClock_Config
Display and TouchGFX
Driver layers
Flash memory and IAP
Segment and sector
Interrupts
NVIC registers
LVGL with SDL2
LVGL ships an SDL2 display and input driver, so a UI can be built and iterated
Mbed TLS
Mbed TLS is the cryptography and TLS library ST integrates through CubeMX. It is
Memory protection unit
The MPU assigns access permissions and memory-type attributes to address ranges.
Startup sequence
From reset to main
STM32CubeIDE
STM32CubeIDE is Eclipse-based, so the general shortcuts and known issues on the
UART and virtual COM port
Most Discovery and Nucleo boards route one USART to the on-board ST-LINK, which