Electronics
Serial bus comparison
UART
UART is the simplest asynchronous link: two wires, no clock, both ends configured to the same bit rate. Its limitations are what the other buses exist to solve:
| Limitation | Usual answer |
|---|---|
| Short range — TTL levels do not survive long cable runs | RS-232 and RS-485 line drivers |
| Low throughput | SPI |
| Point-to-point only, no addressing | I²C, RS-485 multidrop |
Because there is no shared clock, both ends must agree on the bit rate in advance and their clocks must stay within roughly ±2 % of each other. This is why a device running from an uncalibrated internal RC oscillator produces garbled output at high baud rates while working fine at 9600.
Range
| Standard | Typical maximum length | Topology |
|---|---|---|
| UART at TTL levels | < 1 m | Point-to-point |
| RS-232 | 15 m at 19.2 kbit/s, ~30 m at low rates | Point-to-point |
| RS-485 | 1200 m at 100 kbit/s | Multidrop, up to 32 standard unit loads |
Length and speed trade against each other on every one of these — the figures above are the commonly quoted maxima at low bit rates, not simultaneous limits. RS-485 also needs termination resistors at both ends of the cable once the run is long relative to the signal rise time.
Throughput
| Bus | Typical rate | Effective payload |
|---|---|---|
| UART, 115200 baud, 8N1 | 115.2 kbit/s | ~11.25 KiB/s |
| SPI | 10–50 MHz clock | 1.25–6 MB/s and up |
| I²C | 100 kHz / 400 kHz / 3.4 MHz | ~10 / 40 / 340 KiB/s |
The 8N1 framing sends 10 bits per byte — one start bit, eight data bits, one stop bit — so byte throughput is the baud rate divided by 10, not by 8.
SPI has no protocol overhead beyond chip select, so its payload rate is essentially the clock rate divided by 8. The practical ceiling is set by the slave device and by trace length, not by the standard, which does not specify a maximum.
NAND Flash and NOR Flash
| NOR Flash | NAND Flash | |
|---|---|---|
| Read | Fast, true random access, byte-addressable | Page-oriented, higher latency |
| Write / erase | Slower | Faster |
| Execute in place (XIP) | Yes | No — must be copied to RAM first |
| Cost per bit | Higher | Lower |
| Density | Lower | Higher |
| Endurance | ~100k cycles per block | ~1k–100k depending on cell type |
| Bad blocks | None from the factory | Expected; require management |
| Typical use | Firmware, boot code, small configuration stores | Mass storage: SSDs, eMMC, USB drives |
- NOR is chosen when code runs directly out of flash. Its random access and guaranteed-good array are what make execute-in-place possible.
- NAND is chosen for capacity. It needs error-correcting codes (ECC) and bad-block management, normally handled by a flash translation layer in the controller or in software.
Erase granularity matters more than either figure above. Both technologies erase a whole block or sector at a time — see Segment and sector.
PSRAM
PSRAM (pseudo-static RAM) uses DRAM storage cells internally but presents an SRAM-like interface. The refresh logic sits inside the chip, so no external memory controller or refresh scheduling is needed.
- Cell structure: 1T+1C per bit, against 6T for true SRAM — much smaller die, therefore much higher density at a given cost.
- Interface: same as SRAM, or a serial variant (Quad/Octal SPI) on modern parts. No SDRAM-style command sequencing.
- Capacity: from 8/16/32 Mbit parts up to 128 MB. Well above SRAM, below what SDRAM reaches.
- Speed: supports burst mode, so sequential access is reasonable, though random access latency is worse than SRAM.
- Power: substantially lower than SDRAM, which is why battery-powered designs favour it.
- Cost: slightly above SDRAM of the same capacity, far below SRAM.
Typical applications are frame buffers and working memory in phones, handheld devices, media players, GPS receivers and other portable products. Suppliers include Winbond, Micron, AP Memory and ISSI.
Note that "pseudo-static" only refers to the interface. The cells still lose their contents without refresh, so the data is not retained through a power cycle or a deep sleep mode that gates the supply.
Phase-locked loop
A PLL generates an output whose frequency and phase track an input reference. It is what lets a 25 MHz crystal drive a 400 MHz CPU clock.
Skipping rope is a fair analogy: the rope is the reference, your jumping is the output, and the constant small corrections you make to stay in step are the loop.
Components
- Phase detector — compares the phase of the reference against the feedback signal and produces an error signal whose magnitude and sign reflect the difference. The eyes in the analogy.
- Loop filter — a low-pass filter that smooths the error signal into a stable control voltage. Its bandwidth sets how fast the loop locks and how much reference jitter it passes through. The brain.
- Voltage-controlled oscillator (VCO) — produces the output; its frequency moves with the control voltage. The legs.
- Feedback divider — divides the VCO output by N before the phase detector sees it. This is what turns the loop into a frequency multiplier: the loop settles where f_out / N equals f_ref, so f_out = N × f_ref.
Most MCU PLLs add an input divider M and one or more output dividers P, Q and R, giving f_out = f_ref × N / (M × P). The STM32H7 configuration in SystemClock_Config is a direct instance of this: 25 MHz × 160 / 5 = 800 MHz VCO, then P = 2 for a 400 MHz system clock.
Applications
- Frequency synthesis — derive many clocks from one crystal. The dominant use inside microcontrollers and SoCs.
- Clock generation and de-skew — produce a clean, correctly phased clock for the CPU and peripherals.
- Carrier recovery and synchronisation — keep a receiver locked to a transmitter in radio and wired data links.
Practical notes
- The loop takes time to lock. Firmware must wait for the ready flag before switching the system clock over, or the core runs from an unstable clock.
- VCOs have a valid input range. STM32 parts require the reference after the M
divider to land in a specific band, selected through
PLLRGE, and the VCO output band throughPLLVCOSEL. - Output jitter is inherited from the reference and shaped by the loop bandwidth. High-speed interfaces such as USB and Ethernet have jitter budgets that a poorly chosen configuration will violate even though the frequency is correct.